1. Field of the Invention
The present invention relates to a switching circuit and more particularly to a test technique for ATM switches.
2. Description of the Background Art
A data transmission system known as an ATM (Asynchronous Transfer Mode) is employed in a broadband ISDN (Integrated Service Digital Network). The ATM is one of the modes for allotting information in an exchange station when the information is transmitted from a plurality of transmitters, e.g., broadcasting stations to a plurality of receivers, e.g., homes.
In this mode, the information is divided into fixed-length blocks known as cells, which is transmitted or exchanged at high speeds, for example 150 Mbps. A standard cell is composed of signals of 53 bytes. A part of the cell, referred to as a header, includes the information specifying output destinations and the like. The number of bytes is sometimes increased by the additional increase of the information of one cell.
The center of cell exchange operations is ATM switches, which have been formed into circuits in increasing numbers recently. A plurality of cells are often concentrated on a single output destination in the exchange operations. This necessitates the provision of a buffer memory for queuing the cells in the ATM switch. The structures of the ATM switches are typically classified according to the location of the buffer memory in the switch into three types: input buffer type, output buffer type and common buffer type switching systems. The buffer memory is positioned before the switching in the input buffer type switching system. The buffer memory is positioned after the switching in the output buffer type switching system. The cells from respective inputs are multiplexed, and the multiplexed cells are stored in a common buffer memory shaped by respective outputs, in the common buffer type switching system.
There is conceptionally shown in FIG. 9 a structure of the ATM switch of the common buffer type switching system which is taught in 1991 International Solid-State Circuits Conference, Digest of Technical Papers, pp. 242-243. All incoming and outgoing lines 101 and 102 share a single FIFO buffer memory 103. The cells inputted from the incoming lines 101 are written to the FIFO buffer memory 103 through a cell multiplexer 104, and the cells read out of the FIFO buffer memory 103 are outputted to the outgoing lines 102 through a cell demultiplexer 105. The cells to be outputted to the same outgoing line, if inputted from two or more incoming lines, are temporarily held in the FIFO buffer memory 103. When the FIFO buffer memory 103 is full, the cells are discarded.
Such a circuit of the common buffer type switching system must be provided with a large-capacity, high-speed FIFO buffer memory. Since the bit rate is 155.52 Mbps in the broadband ISDN, an 8.times.8 configuration ATM switch needs a throughput of about 1.2 Gbps (150 Mbps.times.8). To minimize a cell discard rate, the FIFO buffer memory must have a capacity for storing a few hundred cells.
FIG. 10 shows in more detail the structure of the ATM switch of FIG. 9. Data are inputted to each incoming line in 4-bit parallel. The cell multiplexer 104 for performing a serial-to-parallel conversion converts the inputted data into 128-bit (4.times.32) parallel data, which are written to the common buffer memory 103. An address generating circuit 106 detects, from the header of the cell, the outgoing line to which the cell is to be outputted and correspondingly specifies the address of the FIFO buffer memory 103. The cell demultiplexer 105 having a capability of a 32:1 parallel-to-serial conversion reconverts the 128-bit parallel data into 4-bit parallel data, which are outputted to the outgoing line. An address control circuit 107 controls the read/write addresses of the FIFO memory in accordance with the address specified by the address generating circuit 106.
The common buffer type switching system is effective in terms of reduction in the total capacity of the buffer memory. However, very high memory access speeds are required for the common buffer type switching system in which the multiplexed input data are written to the large common buffer memory at high speeds and the data are read out of the large common buffer memory at high speeds to be outputted to the outgoing lines.
To eliminate the foregoing drawbacks, a switching system of dividing the buffer memory has been considered. This system enables the access speed of the buffer memory to decrease while maintaining the advantages of the common buffer type switching system.
For achievement of the system, however, a pair of switches of matrix structure must be used. The system has a problem in that a long test pattern is necessary to test a switching circuit including the switches.